4700 CPU SPI Controller
The SPI controller is implemented in the FPGA. This core is found at 0x80004800, and should only be accessed using 16-bit reads/writes.
The table below is the register map for the SPI in the FPGA:
|0x0||Read Only||15||SPI MISO state|
|Read/Write||14||SPI CLK state|
|Read/Write||13:10||Speed - 0 (highest), 1 (1/2 speed), 2 (1/4 speed)...|
|Read/Write||9:8||LUN (0-3 representing the 4 chip selects)|
|Read/Write||7||CS (1 - CS# is asserted)|
|0x2||Read Only||15:0||Previous SPI read data from last write|
|0x8||Read/Write||15:0||SPI read/write with CS# to stay asserted|
|0xa||Read Only||15:0||SPI pipelined read with CS# to stay asserted|
|0xc||Read/Write||15:0||SPI Read/Write with CS# to deassert post-op|
The SPI clk state register should be set when CS# is deasserted. Value 0 makes SPI rising edge (CPOL=0), 1 is falling edge (CPOL=1). This only applies to speed >= 1.
Where the base clock is 75Mhz (extended temp alters this to 50Mhz), speed settings break down as follows:
The pipelined read register is for read bursts and will automatically start a subsequent SPI read upon completion of the requested SPI read. Reading from this register infers that another read will shortly follow and allows this SPI controller "a head start" on the next read for optimum read performance. This register should be accessed as long as there will be at least one more SPI read with CS# asserted to take place.