4700 DIO

From Technologic Systems Manuals

This board uses both CPU and a DIO controller in the FPGA. The CPU DIO typically has 1-7 functions associated with various pins (I2C, PWM, SPI, etc). See the CPU manual CPU manual for the complete listing and for information on how to control these DIO. For purposes of identity, all FPGA DIO will be labelled DIO_n (where n is the DIO pin number), and all CPU dio will be labelled MFP_n.
Bit masking: Any bits not expressly mentioned here should be masked out. Direction setting: 0 is input, 1 is output.

All FPGA DIO are controlled by three distinct register types: Direction, Input Data, and Output Data. To use any DIO pin, the direction register must be set (0 for input, 1 for output), then either the input register may be read, or the output register may be written to. These registers are described in the Syscon memory table.
For example, to write to DIO_0, bit 0 (the LSB) of 0x80004018 (The direction register for DIO_0 through DIO_14) must be set high, then the desired value (high = 1 low = 0) should be written to bit 0 of 0x80004010 (the Output Data register for DIO_0 through DIO_14). Alternatively to read the status of that pin, the Direction Register must be set low, then bit zero of 0x80004020 would reflect the status of that pin.

Full details on CPU pins can be found in the CPU manual, along with mode and mapping assignments specific to the CPU. As this comprises twelve pages of material that must be completely understood, it is best to read the CPU manual carefully before making use of these pins.
The pages of interest in the CPU manual regarding the MFP_n pins start at page A-5 and continue through page A-12 under section A.1. General information for DIO access is given here for convenience: CPU GPIO Register base: 0xD4019000 The offsets table for the CPU GPIO pins is on pages A-7 through A-9. The register description for each pin's register is located on pages A-9 through A-12.

All 60 of the DIO from the FPGA will default to the DIO mode. These pins coming from the FPGA are all 3.3V tolerant. To manipulate these DIO you can access the #Syscon. The initrd also has ts4700.subr which has functions for manipulating the DIO through shell functions:

# If you're in the initrd:
source /ts4700.subr

# If you're in Debian:
source /initrd/ts4700.subr

#Usage: setdiopin <pin> <1,0,Z> <b>
setdiopin 8 0

#Usage: getdiopin <pin>
getdiopin 9
DIO Number Connector Location Alternate Function
0 CN1_93 Offboard IRQ 67
1 CN1_91 Offboard IRQ 68
2 CN1_89 Offboard IRQ 69
3 CN1_87 12.5MHz clock
4 CN1_85 XUART5 CTS, edge counter 0 input
5 CN1_83 Board ID
6 CN1_81 Edge counter 1 input
7 CN1_79 XUART5 TX_EN, ADC_CLK
8 CN1_77 AN_SEL, XUART1 TX_EN
9 CN1_73 External Reset
10 CN1_71 CAN2_TXD, XUART2 TX_EN
11 CN1_69 CAN2_RXD
12 CN1_67 XUART0 TX_EN
13 CN1_65 XUART6 RXD, XUART3_TXEN
14 CN1_63 XUART4_TXEN
15 CN2_97 CAN1_TXD
16 CN2_99 CAN1_RXD
17 CN2_65 SPI_FRM
18 CN2_67 SPI_MOSI
19 CN2_69 SPI_MISO
20 CN2_71 SPI_CLK
21 N/A N/A
22 CN1_97 BUS_WAIT#
23 CN1_99 BUS_BHE#
24 CN1_100 BUS_CS#
25 CN1_98 BUS_DIR, MODE2
26 CN1_96 BUS_ALE#
27 CN1_78 MUX_AD_08
28 CN1_76 MUX_AD_09
29 CN1_74 MUX_AD_10
30 CN1_72 MUX_AD_11
31 CN1_70 MUX_AD_12
32 CN1_68 MUX_AD_13
33 CN1_66 MUX_AD_14
34 CN1_64 MUX_AD_15
35 CN1_94 MUX_AD_00
36 CN1_92 MUX_AD_01
37 CN1_90 MUX_AD_02
38 CN1_88 MUX_AD_03
39 CN1_86 MUX_AD_04
40 CN1_84 MUX_AD_05
41 CN1_82 MUX_AD_06
42 CN1_80 MUX_AD_07
43 N/A N/A
44 N/A N/A
45 N/A N/A
46 N/A N/A
47 N/A N/A
48 CN2_78 XUART0 TXD
49 CN2_80 XUART0 RXD
50 CN2_82 XUART1 TXD
51 CN2_84 XUART1 RXD
52 CN2_86 XUART2 TXD
53 CN2_88 XUART2 RXD
54 CN2_90 XUART3 TXD
55 CN2_92 XUART3 RXD
56 CN2_94 XUART4 TXD
57 CN2_96 XUART4 RXD
58 CN2_98 XUART5 TXD
59 CN2_100 XUART5 RXD