4700 FPGA Functionality
All macrocontrollers feature an FPGA. Any external interfaces called for by the TS-SOCKET specification that are not provided by the CPU are implemented in the FPGA whenever possible. The FPGA is connected to the CPU by a static memory controller, and as a result the FPGA can provide registers in the CPU memory space.
While most common functionality is accessed through layers of software that are already written, some features may require talking directly to the FPGA. Access to the FPGA is done through either the 8-bit or 16-bit memory regions. Code should access 16-bit or 8-bit depending on the access designed for the specific hardware core. For example, the CAN core is 8 bit, the 8 bit MUXBUS space is 8 bit, and some 8 bit cycles are needed for the SPI core if you want to do 8 bit SPI transactions. To access hardware cores in the FPGA, add the offset in the table below to the base address.
|Bit Width||Base Address|
|0x0000||16KB blockram access (for XUART buffer)||16|
|0x4400||ADC registers (for off-board ADC)||16|
|0x4D00||2nd CAN controller||8|
|0x5400||XUART IO registers||16|
|0x8000||32KB MUXBUS space||16/8|