From Technologic Systems Manuals
- ↑ 1.0 1.1 1.2 1.3 The FPGA JTAG pins are not recommended for use and are not supported. See the #FPGA Programming section for the recommended method to reprogram the FPGA.
- ↑ EXT_RESET# is an input used to reboot the CPU. Do not drive active high, use open drain.
- ↑ This is an output which can be manipulated in the #Syscon. This pin can optionally be connected to control a FET to a separate 5V rail for USB to allow software to reset USB devices.
- ↑ OFF_BD_RESET# is an output from the macrocontroller that automatically sends a reset signal when the unit powers up or reboots. It can be connected to any IC on the base board that requires a reset.
- ↑ 5.0 5.1 5.2 5.3 The POWER pins should each be provided with a 5V source.
- ↑ By default DIO9 will reset the board when toggled high. This can be disabled "ts4700ctl --resetswitchoff".
- ↑ 7.0 7.1 The TS-4700 regulates a 3.3V rail which can source up to 700mA. Designs should target a 300mA max if they intend to use other macrocontrollers.
- ↑ This pin is used as a test point to verify the CPU has a correct voltage for debugging
- ↑ 9.0 9.1 9.2 9.3 Most TS-SOCKET systems run Linux, in which case the CPU JTAG bus is not useful and should not be connected. For developers who want to use another operating system, or write "bare-metal" microcontroller-style code, this CPU JTAG debugging interface is made available. If you need to use this interface, please contact Technologic Systems to order a TS-8200 base board with the CPU JTAG connector.
- ↑ This pin is used as a test point to verify the RAM has a correct voltage for debugging
- ↑ This pin is used as a test point for debugging
- ↑ This should be supplied with 5V to power the USB ports.