From Technologic Systems Manuals

The TS-4200 features an 8KB non-volatile SRAM. If a voltage is supplied on V_BAT, the TS-4200 can shut down without losing SRAM data. To communicate with the SRAM, software must read and write the FPGA blockram region, and use NVRAM control registers to initiate block transfers between the FPGA blockram and the SRAM. The NVRAM control register map is as follows:

Offset Bits Usage
0x0 15:2 Reserved
1 power fail. 1 = further transfers are not permitted.
0 busy flag. Indicates transfer is occurring.
0x2 15:3 Reserved
2:1 NVRAM bank used for copy
0 0 = copy NVRAM to blockram
0x4 15:1 Reserved
0 transfer enable register
0x6 15:0 Power fail flag can be cleared by writing 0 to this register.

Data transfers between FPGA blockram and SRAM happen in 2KB blocks. The NVRAM consists of 8KB divided into 4 banks of 2KB. The correct software algorithm for a single transfer is as follows:

  • Make sure the busy flag and power fail flag are not set
  • Program the NVRAM bank register and direction register as desired
  • Set the transfer enable flag
  • Poll the busy flag until it goes high
  • Clear the transfer enable flag

The ts4200ctl utility source code includes a function that demonstrates the above algorithm.