TS-4710 TS-Socket

From Technologic Systems Manuals
CN1 CN2
Name Pin Pin Name
FPGA_JTAG_TMS [1] 1 2 EXT_RESET# [2]
FPGA_JTAG_TCK [1] 3 C 4 EN_USB_5V [3]
FPGA_JTAG_TDO [1] 5 N 6 SDCARD_D2
FPGA_JTAG_TDI [1] 7 1 8 SDCARD_D3
OFF_BD_RESET# [4] 9 10 SDCARD_CMD
Reserved 11 12 SDCARD_3.3V
Reserved 13 C 14 SDCARD_CLK
POWER [5] 15 N 16 POWER [5]
Reserved 17 1 18 SDCARD_D0
LCD_D08 19 20 SDCARD_D1
LCD_D09 21 22 Reserved
LCD_D10 23 C 24 LCD_D0
LCD_D11 25 N 26 LCD_D1
LCD_D12 27 1 28 LCD_D2
POWER [5] 29 30 LCD_D3
LCD_D13 31 32 LCD_D4
LCD_D14 33 C 34 LCD_D5
LCD_D15 35 N 36 V_BAT
LCD_D16 37 1 38 LCD_D6
LCD_D17 39 40 LCD_D7
LCD_D18 41 42 LCD_D21
LCD_D19 43 C 44 LCD_D22
LCD_D20 45 N 46 LCD_D23
POWER [5] 47 1 48 EN_LCD_3.3V
LCD_CLK 49 50 Reserved
LCD_HSYNC 51 52 Reserved
LCD_VSYNC 53 C 54 Reserved
LCD_DE 55 N 56 Reserved
LCD_PWM 57 1 58 Reserved
Reserved 59 60 Reserved
Reserved 61 62 Ground
DIO_14 / XUART4_TXEN 63 C 64 DIO_34 / MUX_AD_15
DIO_13 65 N 66 DIO_33 / MUX_AD_14
DIO_12 67 1 68 DIO_32 / MUX_AD_13
DIO_11 / CAN2_RXD 69 70 DIO_31 / MUX_AD_12
DIO_10 / CAN2_TXD / XUART2 TXEN 71 72 DIO_30 / MUX_AD_11
DIO_9 [6] 73 C 74 DIO_29 / MUX_AD_10
Ground 75 N 76 DIO_28 / MUX_AD_09
DIO_8 / AN_SEL / XUART1 TXEN 77 1 78 DIO_27 / MUX_AD_08
DIO_7 / XUART5 TXEN / ADC_CLK 79 80 DIO_42 / MUX_AD_07
DIO_6 / Edge Counter 1 81 82 DIO_41 / MUX_AD_06
DIO_5 83 C 84 DIO_40 / MUX_AD_05
DIO_4 / XUART5 CTS / Edge Counter 0 85 N 86 DIO_39 / MUX_AD_04
DIO_3 / 12.5MHz Clock 87 1 88 DIO_38 / MUX_AD_03
DIO_2 / Offboard IRQ 69 89 90 DIO_37 / MUX_AD_02
DIO_1 / Offboard IRQ 68 91 92 DIO_36 / MUX_AD_01
DIO_00 / Offboard IRQ 67 93 C 94 DIO_35 / MUX_AD_00
Ground 95 N 96 DIO_26 / BUS_ALE#
DIO_22 / BUS_WAIT# 97 1 98 DIO_25 / MODE2 / BUS_DIR
DIO_23 / BUS_BHE# 99 100 DIO_24 /BUS_CS#
Name Pin Pin Name
ETH_RX+ 1 2 ETH_LEFT_LED
ETH_RX- 3 C 4 ETH_RIGHT_LED
ETH_CT 5 N 6 RED_LED#
ETH_TX+ 7 2 8 GREEN_LED#
ETH_TX- 9 10 MFP_105
ETH_CT 11 12 MFP_106
3.3V [7] 13 C 14 MFP_122
Ground 15 N 16 Reserved
Reserved 17 2 18 Reserved
Reserved 19 20 Reserved
Ground 21 22 Reserved
Reserved 23 C 24 Reserved
Reserved 25 N 26 MFP_49
Reserved 27 2 28 TWI_CLK
HOST_USB_M 29 30 TWI_DAT
HOST_USB_P 31 32 MFP_104
CPU_CORE [8] 33 C 34 AUD_MCLK
USB_OTG_M 35 N 36 AUD_CLK
USB_OTG_P 37 2 38 AUD_FRM
3.3V [7] 39 40 AUD_TXD
Reserved 41 42 AUD_RXD
Reserved 43 C 44 CPU_JTAG_TMS [9]
Ground 45 N 46 CPU_JTAG_TCK [9]
PCIE_TX- [10] 47 2 48 CPU_JTAG_TDI [9]
PCIE_TX+ [10] 49 50 CPU_JTAG_TDO [9]
Ground 51 52 ONE_WIRE/MFP_84
PCIE_RX- [10] 53 C 54 MFP_51
PCIE_RX+ [10] 55 N 56 CAM_MCLK
DDR_1.8V [11] 57 2 58 CAM_D0
Reserved 59 60 CAM_D1
Reserved 61 62 CAM_D2
AVDD_OSC [12] 63 C 64 CAM_D5
SPI_FRM 65 N 66 CAM_D6
SPI_MOSI 67 2 68 CAM_D7
SPI_MISO 69 70 CAM_HSYNC
SPI_CLK 71 72 CAM_VSYNC
Ground 73 C 74 USB_OTG_ID
Reserved 75 N 76 USB_5V_LINE [13]
Reserved 77 2 78 DIO_48 / UART0_TXD
CPU_JTAG_VCC 79 80 DIO_49 / UART0_RXD
CAM_D3 81 82 DIO_50 / UART1_TXD
CAM_D4 83 C 84 DIO_51 / UART1_RXD
CAM_PCLK 85 N 86 DIO_52 / UART2_TXD
CAM_VCLK 87 2 88 DIO_53 / UART2_RXD
MFP_52 89 90 DIO_54 / UART3_TXD
MFP_43 91 92 DIO_55 / UART3_RXD
DEBUG_TXD 93 C 94 DIO_56 / UART4_TXD
DEBUG_RXD 95 N 96 DIO_57 / UART4_RXD
DIO_15 / CAN_TXD 97 2 98 DIO_58 / UART5_TXD
DIO_16 / CAN1 RXD 99 100 DIO_59 / UART5_RXD
  1. 1.0 1.1 1.2 1.3 The FPGA JTAG pins are not recommended for use and are not supported. See the #FPGA Programming section for the recommended method to reprogram the FPGA.
  2. EXT_RESET# is an input used to reboot the CPU. Do not drive active high, use open drain.
  3. This is an output which can be manipulated in the #Syscon. This pin can optionally be connected to control a FET to a separate 5V rail for USB to allow software to reset USB devices.
  4. OFF_BD_RESET# is an output from the macrocontroller that automatically sends a reset signal when the unit powers up or reboots. It can be connected to any IC on the base board that requires a reset.
  5. 5.0 5.1 5.2 5.3 The POWER pins should each be provided with a 5V source.
  6. This defaults to an offboard reset on our carrier boards the 8550, 8500, 8380, 8280, 8290, and 8160. Customer carrier boards can turn on this offboard reset with tshwctl --resetswitchon
  7. 7.0 7.1 The TS-4710 regulates a 3.3V rail which can source up to 700mA. Designs should target a 300mA max if they intend to use other macrocontrollers.
  8. This pin is used as a test point to verify the CPU has a correct voltage for debugging
  9. 9.0 9.1 9.2 9.3 Most TS-SOCKET systems run Linux, in which case the CPU JTAG bus is not useful and should not be connected. For developers who want to use another operating system, or write "bare-metal" microcontroller-style code, this CPU JTAG debugging interface is made available. If you need to use this interface, please contact Technologic Systems to order a TS-8200 base board with the CPU JTAG connector.
  10. 10.0 10.1 10.2 10.3 PCIe is only present on the TS-4710-1066
  11. This pin is used as a test point to verify the RAM has a correct voltage for debugging
  12. This pin is used as a test point for debugging
  13. This should be supplied with 5V to power the USB ports.