TS-4800 DIO

From Technologic Systems Manuals

The TS-4800 has both CPU and FPGA DIO. In our schematics and documentation we will refer to the CPU DIO as GPIO#_#, and the FPGA DIO as DIO_##. Both are accessed through memory mapped registers. All FPGA DIO are controlled by three distinct register types: Direction, Input Data, and Output Data. To use any DIO pin, the direction register must be set (0 for input, 1 for output), then either the input register may be read, or the output register may be written to. These registers are described in the Syscon memory table.

Full details on CPU pins can be found in the CPU manual, along with mode and mapping assignments specific to the CPU. Many of these pins support multiple functions which are described in Chapter 4: "External Signals and Pin Multiplexing". The GPIO functionality is described in chapter 35.

The common usage for these IO is abstracted through tsctl, or using the built in shell scripts:

# This next line is needed if you are in Debian
#source /initrd/ts.subr

# this should already be sourced in the initrd, but if you connect through
# telnet you will need to source it manually:
#source /ts.subr

# The CPU has gpio_ functions for its DIO:

# gpio_dir_get BANK(1..4) DIO_NUM(0..15)  
gpio_dir_get 1 3

# gpio_dir_set BANK(1..4) DIO_NUM(0..15) DIR(0=input,1=output)
gpio_dir_set 1 3 0

# gpio_data_get BANK(1..4) DIO_NUM(0..15)                     
gpio_data_get 1 3

# to output GPIO1_3, set its direction to an output first:
gpio_dir_set 1 3 1

# gpio_data_set BANK(1..4) DIO_NUM(0..15) 0|1
gpio_data_set 1 3 1

# The FPGA DIO has equivalent functions:
# dio_dir_get BANK(1..4) DIO_NUM(0..15)                      
dio_dir_get 1 15

# dio_dir_set BANK(1..4) DIO_NUM(0..15) DIR(0=input,1=output)
dio_dir_set 1 15 0

# dio_data_get BANK(1..4) DIO_NUM(0..15)                     
dio_data_get 1 15

# dio_data_set BANK(1..4) DIO_NUM(0..15) 0|1                 
dio_data_set 1 15 1

This table describes the FPGA DIO banks which match up with our schematic and the rest of our documentation:

DIO Number Bank Bank DIO number
0:15 1 0:15
16:31 2 0:15
32:47 3 0:15
48:55 4 0:7
DIO Number Connector Location Alternate Function
0 CN1_93 Offboard IRQ 275
1 CN1_91 Offboard IRQ 276
2 CN1_89 Offboard IRQ 277
3 CN1_87
4 CN1_85
5 CN1_83
6 CN1_81
7 CN1_79
8 CN1_77
9 CN1_73
10 CN1_71
11 CN1_69
12 CN1_67
13 CN1_65
14 CN1_63
17 CN2_70
18 CN2_64
19 CN2_62
20 CN2_54 24MHz clock (default)
21 CN1_94 MUX_AD_00
22 CN1_92 MUX_AD_01
23 CN1_90 MUX_AD_02
24 CN1_88 MUX_AD_03
25 CN1_86 MUX_AD_04
26 CN1_84 MUX_AD_05
27 CN1_82 MUX_AD_06
28 CN1_80 MUX_AD_07
29 CN1_78 MUX_AD_08
30 CN1_76 MUX_AD_09
31 CN1_74 MUX_AD_10
32 CN1_72 MUX_AD_11
33 CN1_70 MUX_AD_12
34 CN1_68 MUX_AD_13
35 CN1_66 MUX_AD_14
36 CN1_64 MUX_AD_15
37 CN1_96 BUS_ALE#
38 CN1_98 BUS_DIR
39 CN1_100 BUS_CS#
40 CN1_99 BUS_BHE#
41 CN1_97 BUS_WAIT#
42 CN2_69 SPI_MISO
43 CN2_71 SPI_CLK
44 CN2_65 SPI_CS#
45 CN2_67 SPI_MOSI
46 CN2_99 CAN_RXD
47 CN2_97 CAN_TXD
48 CN2_80 XUART0_RXD
49 CN2_78 XUART0_TXD
50 CN2_92 XUART1_RXD
51 CN2_90 XUART1_TXD
52 CN2_96 XUART2_RXD
53 CN2_94 XUART2_TXD
54 CN2_100 XUART3_RXD
55 CN2_98 XUART3_TXD