TS-4800 Motor Core

From Technologic Systems Manuals

The TS-4800 FPGA includes our motor core which can be used for quadrature and PWM.

The PWM values are 0-256 for 0%-100% duty cycle.

Address Bits Access Description
0x0 15-0 Read / Write PWM Channel 0
0x2 15-0 Read/Write PWM channel 1
0x4 15-0 Read/Write PWM Channel 2
0x6 15-0 Read/Write PWM Channel 3
0x8 15-0 Read/Write PWM Channel 4
0xa 15-0 Read/Write PWM Channel 5
0xc 15-0 Read/Write PWM Channel 6
0xe 15-0 Read/Write PWM Channel 7
0x10 15-0 Read Only Quadrature Count #0
0x12 15-0 Read Only Quadrature Count #1
0x14 15-0 Read Only Quadrature Count #2
0x16 15-0 Read Only Quadrature Count #3
0x18 15-0 Read Only Index Pulse Count #0
0x1a 15-0 Read Only Index Pulse Count #1
0x1c 15-0 Read Only Index Pulse Count #2
0x1e 15-0 Read Only Index Pulse Count #3
0x20 3-0 Read/Write H-Bridge Enable Channel 3-0 (LSB is #0)
7-4 Read/Write Index Pulse Enable Channel 3-0 (LSB is #0)
11-8 Read/Write Index Pulse Polarity Channel 3-0 (LSB is #0)
15-12 Read/Write Quadrature Enable Channel 3-0 (LSB is #0)
0x22 15-8 Read Only Quadrature Input Pins 7-0
7-0 Read Only General Input Pins 7-0
0x24 15-4 N/A Reserved
3-0 Read Only Overcurrent Status Channel 3-0

If the quadrature channels are disabled, quadrature counts become free running upcounters and index pulse counts become edge counters. If overcurrent is tripped, H-bridge enable is automatically temporarily deasserted. This acts as nagative feedback keeping current maxed out at approximately the trip point.

If the Syscon motor core enable bit is set, then the following pin overrides apply:

Connector Pin DIO Motor core usage
CN1 93 0 PWM 0
CN1 91 1 PWM 1
CN1 89 2 PWM 2
CN1 87 3 Quadrature 3
CN1 77 8 Quadrature 0
CN1 73 9 Quadrature 1
CN1 92 22 Quadrature 2
CN1 90 23 PWM 3
CN1 88 24 PWM 4
CN1 84 26 PWM 5
CN1 82 27 PWM 6
CN1 80 28 PWM 7