TS-4900 PCB Changelog

From Technologic Systems Manuals
Revision Changes
A
  • Initial Release
B Not released
C
  • Parts moved away from mounting holes
  • U4-K23(EIM_EB1) and U4 H21(DIO_10) swapped for offboard EIM Bus.
  • 5 LVDS pairs added to CN2 in reserved pins
  • CPU JTAG removed from CN2 for LVDS pairs
    • Available on testpoints
  • Audio MCLK changed to CN2-54
  • Add PU resistor on PHY reset
  • FET clamp for 3.3V
  • FET switch for RTC power
  • Added bias resister for PCIe clock
  • CN2 DIO same as REV A except:
    • CN2_56 is CSI0_DAT17, REV A was GPIO_5
    • CN2_58 is SD4_DAT7, REV A was GPIO_6
    • CN2_60 is SD3_RST, REV A was GPIO_9
  • CPU pin A20 (SD4_DAT3) is strapped low to indicate new revision.
  • CTS/RTS both connected to FPGA so a uart with full control signals can be routed to bluetooth.
D
  • Moved components to create a clearance of 4.2mm around the CPU for the heatsink
  • Changed eMMC to 153 ball version to fit larger eMMC disks
  • Added EIM Byte Enable signal to CN1 pin 22 based on build option.
  • FPGA ball P4 is now used to enable SD card 3.3V power.
  • Allow FPGA_SPI_CS# to be biased with new resistor for OTP modes
  • FPGA_SPI_CS# is now brought out to CN2_34 which was previously a no connect.
  • i.MX6 ball L6 is connected to ground to detect the new revision. U-boot includes the PCB revision as a variable.
E
  • LSR TIWI-BLE Replaced with Silex SX-SDMAC2832S+