The TS-7600 CPU and FPGA provide real-world DIO. The CPU DIO typically have up to 4 functions associated with various pins (I2C, PWM, SPI, etc); see the CPU manual CPU manual for the complete listing and for information on how to control these DIO. This section only lists FPGA DIO.
All FPGA DIO are controlled by three distinct register types: Direction, Input Data, and Output Data. To use any DIO pin, the direction register must be set (0 for input, 1 for output), then either the input register may be read, or the output register may be written to. These registers are described in the Syscon section.
For example, to write to DIO_0, the corresponding bit in the Direction register needs to be set in order to make the pin an output. At this point, the pin will reflect the state of the corresponding bit in the Output register, with a 12mA drive strength. Under most circumstances, the Input register will reflect the Output register if the DIO is set to an output. If the pin is overdriven however, the Input register may read a different value. Clearing a corresponding bit in the Direction register will turn the DIO pin in to a high impedance input with a weak pullup internal to the FPGA, this pin state can be read from the Input register.
The TS-7600 FPGA also contains our EVGPIO core, event driven GPIO. This allows for atomic setting of DIO pins (no need to read-modify-write whole registers) as well as setting up pins to generate interrupts on state changes. See the EVGPIO and Interrupts sections for more information.
The DIO of the TS-7600 are numbered to correspond with pin numbers of both the 44-pin header and the 26-pin header, there are 70 pins total with 54 usable as DIO pins. The pin numbers in the table below count from 1 to 44 on the 44-pin header, and 45 to 70 on the 26-pin header.
All 69 of the DIO from the FPGA will default to the DIO mode. These pins coming from the FPGA are all 3.3V tolerant. To manipulate these DIO you can access the Syscon, either through tshwctl or a custom application. DIO pins that are not listed do not have an FPGA DIO connected to them, see the 44-pin header and the 26-pin header sections to evaluate what a specific pin is designated as.
|DIO #||Pin #||Alternate Function|
|5||44_5||MODE2, XUART0 TX|
|36||44_36||XUART7 RX, LRADC1|
|37||44_37||XUART0 TXEN, LRADC2|
|38||44_38||XUART3 TXEN, LRADC3|
|39||44_39||XUART4 TXEN, LRADC4|
|68||N/A||Eth Amber LED |
|69||N/A||USB power |
- When Direction is set, LED reflects state of Output reg. When Direction is clear, LED reflects LINK light from Ethernet PHY
- When Direction is set, Output bit controls power to the USB host ports