TS-8551-socket

From Technologic Systems Manuals

The TS-SOCKET SoM devices all use 2 high density 100 pin connectors for power and all I/O. These follow a common pinout for various external interfaces so new modules can be switched in to an application in order to lower power consumption or use a more powerful processor. The male connector is on the baseboard, and the female connector is on the SoM. The datasheet for the baseboard's male connector can be found here. Connectors can be ordered from the SoM's product page as CN-TSSOCKET-M-10 for a 10 pack, or CN-TSSOCKET-M-100 for 100 pieces, or from the vendor of your choice; the part is an FCI 61083-102402LF.

TS-Socket

In our schematics and our table layout below, we refer to pin 1 from the male connector on the baseboard.


Example Baseboard


On the TS-8551, the entirety of both high-density connectors are broken out in to 0.1" spaced 2x25 pin headers. There are 4 of these in total, one each for CN1 odd numbered pins, CN1 even numbered pins, CN2 even numbered pins, and CN2 odd numbered pins. They are labeled on the silkscreen every 10 pins, with the first 2 and last 2 pins also being labeled.

Note that the below pinout is from the perspective of the TS-8551. However, the links for each pin will link to the relevant section in this manual. When designing a custom baseboard, it is advised to consider both the TS-8551's TS-SOCKET pinout and functions as well as the target SoM's pinout. For details on a specific SoM's interface, see that device's manual.

CN1 CN2
Name Pin Pin Name
FPGA_JTAG_TMS [1] 1 2 EXT_RESET# [2]
FPGA_JTAG_TCK [1] 3 C 4 EN_USB_5V [3]
FPGA_JTAG_TDO [1] 5 N 6 NC
FPGA_JTAG_TDI [1] 7 1 8 NC
OFF_BD_RESET# [4] 9 10 NC
Microcontroller C2 CLK [5] 11 12 NC
Microcontroller C2 DAT [5] 13 C 14 NC
5 V Power to SoM [6] 15 N 16 5 V Power to SoM [6]
No Charge Jumper / GPIO [7] 17 1 18 NC
U-Boot Jumper / GPIO [8] 19 20 NC
GPIO 21 22 FORCE_PWR_ON# [9]
GPIO 23 C 24 GPIO
GPIO 25 N 26 GPIO
GPIO 27 1 28 GPIO
5 V Power to SoM [6] 29 30 GPIO
GPIO 31 32 GPIO
GPIO 33 C 34 GPIO
GPIO 35 N 36 V_BAT
GPIO 37 1 38 GPIO
GPIO 39 40 GPIO
GPIO 41 42 GPIO
GPIO 43 C 44 GPIO
GPIO 45 N 46 GPIO
5 V Power to SoM [6] 47 1 48 GPIO
GPIO 49 50 USB_OTG_5V [10]
GPIO 51 52 BOOT_MODE_0 [11]
GPIO 53 C 54 NC
GPIO 55 N 56 NC
GPIO 57 1 58 GPIO
GPIO 59 60 GPIO
GPIO 61 62 Ground
GPIO 63 C 64 GPIO
GPIO 65 N 66 GPIO
RS-485 TX Enable / GPIO 67 1 68 GPIO
GPIO 69 70 GPIO
GPIO 71 72 GPIO
U-Boot Push Switch / GPIO 73 C 74 GPIO
Ground 75 N 76 GPIO
GPIO 77 1 78 GPIO
GPIO 79 80 GPIO
GPIO 81 82 GPIO
Board ID Data Out to SoM 83 C 84 GPIO
GPIO 85 N 86 GPIO
GPIO 87 1 88 GPIO
GPIO 89 90 GPIO
GPIO 91 92 GPIO
GPIO 93 C 94 GPIO
Ground 95 N 96 GPIO
GPIO 97 1 98 SD Boot Jumper [12] / GPIO
GPIO 99 100 GPIO
Name Pin Pin Name
Port 0 RX+ [13] / Port 0 BD_DA+ 1 2 Port 0 ACT_LED
Port 0 RX- [13] / Port 0 BD_DA- 3 C 4 Port 0 SPEED_LED
Port 0 CT 5 N 6 RED_LED#
Port 0 TX+ [13] / Port 0 BD_DB+ 7 2 8 GREEN_LED#
Port 0 TX- [13] / Port 0 BD_DB-+ 9 10 Port 1 ACT_LED
Port 0 CT 11 12 GPIO
3.3 VDC output from SoM 13 C 14 Ground
Ground 15 N 16 Port 1 RX+
Port 0 BD_DC+ 17 2 18 Port 1 RX-
Port 0 BD_DC- 19 20 Port 1 CT
Ground 21 22 Port 1 TX+
Port 0 BD_DD+ 23 C 24 Port 1 TX-
Port 0 BD_DD- 25 N 26 Ground
NC 27 2 28 I2C CLK
USB_HOST_M 29 30 I2C DAT
USB_HOST_P 31 32 GPIO
Ground 33 C 34 GPIO
USB_OTG_M 35 N 36 CPU_JTAG_TDI [14]
USB_OTG_P 37 2 38 CPU_JTAG_TDO [14]
3.3 VDC output from SoM 39 40 CPU_JTAG_TRST# [14]
SATA TX+ 41 42 CPU_JTAG_TCK [14]
SATA TX- 43 C 44 Ground
Ground 45 N 46 NC
SATA RX- 47 2 48 NC
SATA RX+ 49 50 Ground
Ground 51 52 GPIO
NC 53 C 54 CPU_JTAG_TMS [14]
NC 55 N 56 GPIO
SSD_PRESENT# 57 2 58 GPIO
NC 59 60 GPIO
NC 61 62 GPIO
1.8 VDC output from SoM [15] 63 C 64 GPIO
SPI CS# 65 N 66 GPIO
SPI MOSI 67 2 68 GPIO
SPI MISO 69 70 GPIO
SPI CLK 71 72 GPIO
Ground 73 C 74 USB_OTG_ID
SuperCap V+ 75 N 76 USB_OTG_5V [10]
SuperCap V+ 77 2 78 UART0 TXD [16]
3.3 VDC output from SoM 79 80 UART0 RXD [16]
SuperCap V+ 81 82 UART1 TXD [16]
SuperCap V+ 83 C 84 UART1 RXD [16]
Ground 85 N 86 UART2 TXD
SuperCap Junction 87 2 88 UART2 RXD
SuperCap Balance Drive 89 90 UART3 TXD
GPIO 91 92 UART3 RXD
DEBUG TXD 93 C 94 UART4 TXD
DEBUG RXD 95 N 96 UART4 RXD
CAN TXD 97 2 98 UART5 TXD
CAN RXD 99 100 UART5 RXD
  1. 1.0 1.1 1.2 1.3 The FPGA JTAG pins are not recommended for use and are not supported.
  2. EXT_RESET# is an input used to reboot the CPU. Do not drive active high, use open drain.
  3. This is an output which can be manipulated as a GPIO. This pin can optionally be connected to control a FET to a separate 5 V rail for USB to allow software to reset USB devices.
  4. OFF_BD_RESET# is an output from the SoM that automatically sends a reset signal when the unit powers up or reboots. It can be connected to any IC on the base board that requires a reset.
  5. 5.0 5.1 This interface is for programming the on-board microcontroller of the SoM, this should be left unconnected on a baseboard.
  6. 6.0 6.1 6.2 6.3 The power pins should each be provided with a 5 V source.
  7. Connect to a 1 kohm pull down to disable Supercapacitor charging on compatible SoMs. Can be used as GPIO after boot.
  8. Connect to a 1 kohm pull down to enter the U-Boot shell at power on on compatible SoMs. Can be used as GPIO after boot.
  9. When low, overrides the microcontroller power control and enables 5 V rail on the SoM. Leave unconnected for normal use.
  10. 10.0 10.1 Allows the supervisory microcontroller to measure USB VBUS for the OTG port.
  11. Normally NC or pulled to ground via 1 kohm resistor. Optionally can be switched/jumpered to pull to 3.3 V through a 1 kohm resistor; this allows other booting options provided by SoM. Not all SoMs honor this pin.
  12. Pull to ground through 1 kohm resistor to boot to SD. Leave floating to boot from on-board media. Do not connect directly to ground or 3.3 V or baseboard ID will no longer function.
  13. 13.0 13.1 13.2 13.3 The Ethernet jack on the TS-8551 is rated for 1000Base-T operation, but is compatible with 10/100Base-TX PHYs
  14. 14.0 14.1 14.2 14.3 14.4 The CPU JTAG pins are not recommended for use and are not supported.
  15. Not output from every SoM.
  16. 16.0 16.1 16.2 16.3 Do not connect to the TTL interface for this UART that is present on the CN breakout pin headers. Doing so may damage the SoM or the connected hardware