TS-8900-dioheader

From Technologic Systems Manuals

The DIO is controlled through manipulation of the TS-8900 FPGA registers.

Header
39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
Pinout
Pin Name Notes
1 N/A Not Connected
2 N/A Not Connected
3 Ground
4 N/A Not Connected
5 N/A Not Connected
6 N/A Not Connected
7 N/A Not Connected
8 N/A Not Connected
9 SPI_MOSI Controlled by tsctl
10 3.3V Do not draw more than 12mA
11 N/A Not Connected
12 BUF_SPI_MOSI
13 BUF_SPI_CS1#
14 BUF_SPI_CLK
15 5V
16 EXT_RESET# Power cycle the whole board
17 N/A Not Connected
18 Ground
19 N/A Not Connected
20 N/A Not Connected
21 IN_0
22 N/A Not Connected
23 IN_1
24 N/A Not Connected
25 IN_2
26 OUT_7
27 IN_3
28 OUT_6
29 IN_4
30 OUT_5
31 IN_5
32 OUT_4
33 IN_6
34 OUT_3
35 IN_7
36 OUT_2
37 I2C_DAT See tsctl for usage.
38 OUT_1
39 I2C_CLK
40 OUT_0