TS-8900-registermap

From Technologic Systems Manuals
Top level decode
Offset Description
0x0000 Syscon
0x0040 SPI Core (to #Phase Change Memory
0x0080 Touchscreen Controller
0x0000 PC/104 16 bit IO
0x0400 PC/104 16 bit MEM
0x0800 PC/104 8 bit IO
0x0c00 PC/104 8 bit MEM
0x1000 SRAM page access
Note: The PC104 standard specifies that the first 0x100 of the IO and MEM regions are reserved. Below 0x100 on the IO or MEM regions will be used for other registers and cannot be used for custom projects.
Syscon
Address Bits Access Description
0x0 15-0 Read Only Board ID (0x8900)
0x02 15-8 Read Only 8 digital inputs
7-4 Read Only Custom load ID (0 is standard 8900)
3-0 Read Only FPGA Revision
0x04 15-8 Read/Write 8 digital outputs
7-4 Read Only Reserved
3 Read/Write Tagmem CLK
2 Read/Write Tagmem SI
1 Read/Write Tagmem CNS
0 Read/Write Tagmem SO
0x6 15-0 Read/Write SRAM page register
0x8 15-0 Read/Write PC104 bits 15-0 GPIO override
0xa 15-9 Read Only Reserved
8 Read-Write PC104 bit 16 override
7-0 Read-Write ISA data lines 15-8 override
0xc 15-0 Read/Write GPIO Output values
0xe 15-9 Read Only Reserved
8 Read/Write PC104 bit 16 output values
7-0 Read/Write ISA data lines 15-8 output values
0x10 15-0 Read/Write PC104 bits 15-0 data direction
0x12 15-9 Read Only Reserved
8 Read/Write PC104 bit 16 data direction
7-0 Read/Write ISA Data lines 15-8 data direction
0x14 15-0 Read/Write PC104 bits 15-0 GPIO input values
0x16 15-9 Read Only Reserved
8 Read Only PC104 bit 16 input values
7-0 Read Only ISA data lines 15-8 input values