4710 FPGA bitstreams

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The FPGA has the capability to be reloaded on startup and reprogram itself with different configurations. The default bitstream is hardcoded into the FPGA, but the soft reloaded bitstreams can be placed in /ts/ts<model>-fpga.vme.gz on the Debian root to make the board load the bitstream on startup. If we do not have a configuration you need, you can build a new bitstream, or contact us for our engineering services.

Bitstream XUARTs CAN Touchscreen SPI ADC
Default (8K LUT) 0-6 On On On Off
ts4710-fpga-rev4-default-ADC.vme.bz2 0-6 On On On On