The source is available here.
We have prepared the opencore projects which gives you the ability to reprogram the FPGA while either preserving or removing our functionality as you choose. The code sources are in verilog, and we use Lattice Diamond to generate the JEDEC file. You can download Lattice Diamond from their site. You can request a free license, and it will run in either Windows or Linux.
Once you have generated the JEDEC file, we have an application called called jed2vme which can be run from an x86 linux system, or directly on the board. Take the resulting vme file and gzip it. To execute this directly on the TS-7500 you can simply save it in the ramdisk in '/ts7500_bitstream.vme.gz'. On startup your bitstream will be loaded.
The linuxrc script will call 'ts7500ctl --loadfpga=ts7500_bitstream.vme.gz', so you can also use that command also to load the bitstream at any time.