From Technologic Systems Manuals
Revision as of 09:36, 28 July 2011 by Mark (talk | contribs)

The source is available here.

We have prepared the opencore projects which gives you the ability to reprogram the FPGA while either preserving or removing our functionality as you choose. The code sources are in verilog, and we use Lattice Diamond to generate the JEDEC file. You can download Lattice Diamond from their site. You can request a free license, and it will run in either Windows or Linux.

Once you have generated the JEDEC file, we have an application called called jed2vme which can be run from an x86 linux system, or directly on the board. You must use this copy we provide as it is modified to force the bitstream to be written to SRAM. Using the jed2vme provided by Lattice can brick the board. Take the resulting vme file and gzip it. To execute this directly on the TS-7500 you can simply save it in the ramdisk in '/ts7500_bitstream.vme.gz'. On startup your bitstream will be loaded.

The linuxrc script will call 'ts7500ctl --loadfpga=ts7500_bitstream.vme.gz', so you can also use that command also to load the bitstream at any time. The FPGA contains flash memory which contains Technologic System's default FPGA SRAM load. The "ts7500ctl --loadfpga" will not overwrite the flash memory of the FPGA and will only load the SRAM contents of the FPGA, making for an unbrickable system if something should go wrong. If something does go wrong, you can restore the onboard flash via the offboard flash or microSD card.