7700 FPGA Programming
|Note:||We do not provide support for the opencores under our free support, however we do offer custom FPGA programming services. If interested please contact us.|
We provide an open version of the Verilog project that contains the functionality of the default FPGA bitstream. The FPGA bitstream is built using Lattice Diamond which is free and runs under Windows or Linux (Redhat). This allows you to modify the verilog and create a jedec file with your custom logic. The jedec is converted to a vme file which is loaded from the SD card and used to reprogram the SRAM of the FPGA on every startup. This requires approximately a second during startup to reprogram, but allows you to recover by removing the bitstream file from the SD card in the case of a faulty bitstream.
The opencore FPGA sources are available here. Custom logic can be built by implementing a wishbone compatible core, or by extending the cores we already have connected.
The ts7700_top.v file is used to connect all of the wishbone cores, and map any DIO. The syscon.v is used for most common system configuration registers. As a simple example these next steps will modify the custom load register located at 0x2a in the syscon.v.
Open up the Lattice diamond tools and open the .ldf file to open the project. On the bottom left there are 3 tabs to control the left panel (Files, Process, and Hierarchy). Go to Files, and double click syscon.v. Around line 40 is:
localparam [3:0] revision = 4'h2; localparam [15:0] custom = 16'h0000;
You can edit the custom value to:
localparam [15:0] custom = 16'h0001;
The custom register is not used by any default software and is a safe register to use for a custom version number. The default bitstream will always use 0.
Save the file and go to the "Process" tab. Double click "Place & Route Trace" to begin synthesizing the bitstream. This will take approximately 5-10 minutes. Once this is finished open the "Reports" tab from the top open file list. Under "Analysis Reports" click on "Place & Route Trace". This is used to verify timing of your build. Under "Preference Summary" make sure none of the clock domains list errors. If timing is not met this will cause seemingly random issues with the bitstream which will usually present first as SD corruption.
Once the timing has been verified, double click "JECEC File" on the "Process" tab to build the jed file. Once this is finished there will be a "ts7700_opencore.jed" in the project folder. In order for the board to use this it must be converted to a vme file. This is generated using "jed2vme":
jed2vme ts7700_opencore.jed | bzip2 > ts7700-fpga.vme.bz2
|WARNING:||Generating a VME using other Lattice's tools can generate a flash bitstream which will render your board unbootable.|
Once this is built it should be placed on the second partition of the SD card as "/ts/ts<model>-fpga.vme.bz2" This should match your macrocontroller's model such as "/ts/ts7700-fpga.vme.bz2".
Once it is loaded on the SD card the board can be booted normally. The green and red LEDs will shut off during programming, and then turn back on after the bitstream has been reloaded. Commands should not be run during reload since issuing a bus cycle during programming can interfere with timing and cause the reload to fail. Once it has reloaded you can use devmem to verify the register has changed:
devmem 0x8000402a 16
On the default bitstream this should return "0x0000", or "0x0001" if modified as suggested above.