The FPGA has the capability to be reloaded on startup and reprogram itself with different configurations. The default bitstream is hardcoded into the FPGA, but the soft reloaded bitstreams can be placed in /ts4800_bitstream.vme.gz on the initrd root to make the board load the bitstream on startup. If we do not have a configuration you need, you can build a new bitstream, or contact us for our engineering services.
We have had several changes to the FPGA during the lifetime for fixing any bugs that are found. You can use an opencore and reload the bitstream to get the latest fixes, though bootrom updates can only be applied by submitting an RMA for your board.
* Removed "IRQ Enable" bits from syscon. Linux handles this automatically. * Removed the unused mode3 bit * CAN enable bit automatically set when accessing CAN registers * XUART enable bit automatically set when accessing XUART registers * Removed debug registers and other unused bits * Cleaned up mode latching code * Forced wb_spi to always be 8bit for data reg access, removes need of 16 to 8 bridge * Dblstor routines added to bootrom * Boot behavior to fallback to NAND if SD boot is on and SD fails * Fixed early LED behavior in bootrom
* CAN resync fixups * PC/104 muxed IRQs working * MUXBUS bridge fixups, arbiter, cleanup * Added CAN and PC/104 IRQ enables * Added counters * Added RS-422 enables * Added ADC core * Added memwindow for 8bit MUXBUS access * WishBone resync fixups
|5||Decrease counter code size|
|4||Bootrom fix for framebuffer reboot issue.|