Difference between revisions of "TS-8100 DIO header"

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The TS-8100 includes a 2x8 0.1" pitch header with 8 DIO, I2C, and SPI.  Most DIO on this header are rated for 3.3V and are not tolerant of 5V IO.  The only exception is SPI_MOSI which is 5V tolerant.  The DIO on this baseboard can be accessed by manipulating the [[#Baseboard Register Map|TS-8100 Register Map]], or using [[#tsctl|tsctl]].
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The TS-8100 includes a 2x8 0.1" pitch header with 8 DIO, I2C, and SPI.  Most DIO on this header are rated for 3.3V and are not tolerant of 5V IO.  The only exception is SPI_MOSI which is 5V tolerant.  The DIO on this baseboard can be accessed by manipulating the [[#TS-8100_Register_Map|TS-8100 Register Map]], or using [[#tsctl|tsctl]].
 
 
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If you receive a "socket error", see the [[#tsctl|tsctl]] chapter for information on setting up and running the tsctl server.
 
  
 
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Latest revision as of 15:35, 9 July 2015

The TS-8100 includes a 2x8 0.1" pitch header with 8 DIO, I2C, and SPI. Most DIO on this header are rated for 3.3V and are not tolerant of 5V IO. The only exception is SPI_MOSI which is 5V tolerant. The DIO on this baseboard can be accessed by manipulating the TS-8100 Register Map, or using tsctl.

Pinout Header
Pin Name Notes
1 8100_DIO_1 Pulled high by R124
2 Ground
3 8100_DIO_3 Pulled high by R123
4 I2C_CLK
5 8100_DIO_5 Pulled high by R122
6 SPI_CS
7 8100_DIO_7 pulled high by R121
8 I2C_DAT
9 8100_DIO_9 Pulled high by R120
10 SPI_MISO
11 8100_DIO_11 Pulled high by R119
12 SPI_MOSI
13 8100_DIO_13 Pulled high by R118
14 SPI_CLK
15 8100_DIO_15 Pulled high by R117
16 CPU_3.3V

TS-8100-DIO.png